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| semiconductor group 1 16m 72-bit dynamic ram module (ecc - module ) hym 72v1600gs-50/-60 hym 72v1610gs-50/-60 preliminary information ? 16 777 216 words by 72-bit ecc - mode organization ? fast access and cycle time 50 ns access time 90 ns cycle time (-50 version) 60 ns access time 110 ns cycle time (-60 version) ? fast page mode capability with 35 ns cycle time (-50 version) 40 ns cycle time (-60 version) ? single + 3.3v ( 0.3v) supply ? low power dissipation max. 6480 mw active (-50 version) max. 5832 mw active (-60 version) cmos C 108 mw standby lvttl C 180 mw standby ? cas -before-ras refresh, ras -only-refresh ? 18 decoupling capacitors mounted on substrate ? all inputs, outputs and clock fully lvttl & lvcmos compatible ? 4 byte interleave enabled, dual address inputs (a0/b0) ? buffered inputs excepts ras and dq ? 168 pin, dual read-out, single in-line memory module ? utilizes eighteen 16m 4 -drams and four bicmos 8-bit buffers/line drivers vt244a ? two versions : hym 72v1600gs with tsopii-components (4 mm thickness) hym 72v1610gs with soj-components (9 mm thickness) ? 8192 refresh cycles / 128 ms with 13 / 11 addressing ? gold contact pad ? double sided module with 38.1 mm (1500 mil) height 1 11.95
semiconductor group 1 16m 72-bit dynamic ram module (ecc - module ) hym 72v1600gs-50/-60 hym 72v1610gs-50/-60 preliminary information ? 16 777 216 words by 72-bit ecc - mode organization ? fast access and cycle time 50 ns access time 90 ns cycle time (-50 version) 60 ns access time 110 ns cycle time (-60 version) ? fast page mode capability with 35 ns cycle time (-50 version) 40 ns cycle time (-60 version) ? single + 3.3v ( 0.3v) supply ? low power dissipation max. 6480 mw active (-50 version) max. 5832 mw active (-60 version) cmos C 108 mw standby lvttl C 180 mw standby ? cas -before-ras refresh, ras -only-refresh ? 18 decoupling capacitors mounted on substrate ? all inputs, outputs and clock fully lvttl & lvcmos compatible ? 4 byte interleave enabled, dual address inputs (a0/b0) ? buffered inputs excepts ras and dq ? 168 pin, dual read-out, single in-line memory module ? utilizes eighteen 16m 4 -drams and four bicmos 8-bit buffers/line drivers vt244a ? two versions : hym 72v1600gs with tsopii-components (4 mm thickness) hym 72v1610gs with soj-components (9 mm thickness) ? 8192 refresh cycles / 128 ms with 13 / 11 addressing ? gold contact pad ? double sided module with 38.1 mm (1500 mil) height 1 11.95 semiconductor group 2 hym72v1600/10gs-50/-60 16m x 72-ecc module the hym 72v1600/10gs-50/-60 is a 128 mbyte dram module organized as 16 777 216 words by 72-bit in a 168-pin, dual read-out, single-in-line package comprising eighteen hyb 3164400bt/bj 16m 4 drams in 500 mil wide tsopii or soj- packages mounted together with eighteen 0.2 m f ceramic decoupling capacitors on a pc board. all inputs except ras and dq are buffered by using four bicmos 8-bit buffers/line drivers. each hyb 3164400bt/bj is described in the data sheet and is fully electrically tested and processed according to siemens standard quality procedure prior to module assembly. after assembly onto the board, a further set of electrical tests is performed. the density and speed of the module can be detected by the use of presence detect pins. ordering information pin names presence-detect and id-pin truth table: note: 1 = high level ( driver output) , 0 = low level (driver output) for pde active ( ground) . for pde at a high level all pd terminal are in tri-state. type ordering code package descriptions hym 72v1600gs-50 l-dim-168-7 3.3v 50ns dram module hym 72v1600gs-60 q67100-q2079 l-dim-168-7 3.3v 60ns dram module hym 72v1610gs-50 l-dim-168-7 3.3v 50ns dram module hym 72v1610gs-60 q67100-q2080 l-dim-168-7 3.3v 60ns dram module a0-a12,b0 address input dq0 - dq71 data input/output ras0 , ras2 row address strobe cas0 , cas2 column address strobe we0 , we2 read / write input oe0 , oe2 output enable vcc power (+3.3 volt) vss ground pd1 - pd8 presence detect pins pde presence detect enable id0 , id1 id indentification bit n.c. no connection module id0 id1 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 hym 72v1600gs-50 vss vss 1 1 110000 hym 72v1600gs-60 vss vss 1 1 110110 semiconductor group 2 hym72v1600/10gs-50/-60 16m x 72-ecc module the hym 72v1600/10gs-50/-60 is a 128 mbyte dram module organized as 16 777 216 words by 72-bit in a 168-pin, dual read-out, single-in-line package comprising eighteen hyb 3164400bt/bj 16m 4 drams in 500 mil wide tsopii or soj- packages mounted together with eighteen 0.2 m f ceramic decoupling capacitors on a pc board. all inputs except ras and dq are buffered by using four bicmos 8-bit buffers/line drivers. each hyb 3164400bt/bj is described in the data sheet and is fully electrically tested and processed according to siemens standard quality procedure prior to module assembly. after assembly onto the board, a further set of electrical tests is performed. the density and speed of the module can be detected by the use of presence detect pins. ordering information pin names presence-detect and id-pin truth table: note: 1 = high level ( driver output) , 0 = low level (driver output) for pde active ( ground) . for pde at a high level all pd terminal are in tri-state. type ordering code package descriptions hym 72v1600gs-50 l-dim-168-7 3.3v 50ns dram module hym 72v1600gs-60 q67100-q2079 l-dim-168-7 3.3v 60ns dram module hym 72v1610gs-50 l-dim-168-7 3.3v 50ns dram module hym 72v1610gs-60 q67100-q2080 l-dim-168-7 3.3v 60ns dram module a0-a12,b0 address input dq0 - dq71 data input/output ras0 , ras2 row address strobe cas0 , cas2 column address strobe we0 , we2 read / write input oe0 , oe2 output enable vcc power (+3.3 volt) vss ground pd1 - pd8 presence detect pins pde presence detect enable id0 , id1 id indentification bit n.c. no connection module id0 id1 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pd8 hym 72v1600gs-50 vss vss 1 1 110000 hym 72v1600gs-60 vss vss 1 1 110110 semiconductor group 3 hym72v1600/10gs-50/-60 16m x 72-ecc module pin configuration pin # symbol pin # symbol pin # symbol pin # symbol 1 vss 43 vss 85 vss 127 vss 2 dq0 44 oe2 86 dq36 128 nc 3 dq1 45 ras2 87 dq37 129 nc 4 dq2 46 cas4 88 dq38 130 nc 5 dq3 47 nc 89 dq39 131 nc 6 vcc 48 we2 90 vcc 132 pde 7 dq4 49 vcc 91 dq40 133 vcc 8 dq5 50 nc 92 dq41 134 nc 9 dq6 51 nc 93 dq42 135 nc 10 dq7 52 dq18 94 dq43 136 dq54 11 dq8 53 dq19 95 dq44 137 dq55 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq20 97 dq45 139 dq56 14 dq10 56 dq21 98 dq46 140 dq57 15 dq11 57 dq22 99 dq47 141 dq58 16 dq12 58 dq23 100 dq48 142 dq59 17 dq13 59 vcc 101 dq49 143 vcc 18 vcc 60 dq24 102 vcc 144 dq60 19 dq14 61 nc 103 dq50 145 nc 20 dq15 62 nc 104 dq51 146 nc 21 dq16 63 nc 105 dq52 147 nc 22 dq17 64 nc 106 dq53 148 nc 23 vss 65 dq25 107 vss 149 dq61 24 nc 66 dq26 108 nc 150 dq62 25 nc 67 dq27 109 nc 151 dq63 26 vcc 68 vss 110 vcc 152 vss 2 7 we0 6 9 dq 28 111 n c 15 3 d q6 4 28 cas0 70 dq29 112 nc 154 dq65 29 nc 71 dq30 113 nc 155 dq66 30 ras0 72 dq31 114 nc 156 dq67 31 oe0 73 vcc 115 nc 157 vcc 32 vss 74 dq32 116 vss 158 dq68 33 a0 75 dq33 117 a1 159 dq69 34 a2 76 dq34 118 a3 160 dq70 35 a4 77 dq35 119 a5 161 dq71 36 a6 78 vss 120 a7 162 vss 37 a8 79 pd1 121 a9 163 pd2 38 a10 80 pd3 122 a11 164 pd4 39 a12 81 pd5 123 nc 165 pd6 40 vcc 82 pd7 124 vcc 166 pd8 41 nc 83 id0 (vss) 125 nc 167 id1 (vss) 42 nc 84 vcc 126 b0 168 vcc semiconductor group 3 hym72v1600/10gs-50/-60 16m x 72-ecc module pin configuration pin # symbol pin # symbol pin # symbol pin # symbol 1 vss 43 vss 85 vss 127 vss 2 dq0 44 oe2 86 dq36 128 nc 3 dq1 45 ras2 87 dq37 129 nc 4 dq2 46 cas4 88 dq38 130 nc 5 dq3 47 nc 89 dq39 131 nc 6 vcc 48 we2 90 vcc 132 pde 7 dq4 49 vcc 91 dq40 133 vcc 8 dq5 50 nc 92 dq41 134 nc 9 dq6 51 nc 93 dq42 135 nc 10 dq7 52 dq18 94 dq43 136 dq54 11 dq8 53 dq19 95 dq44 137 dq55 12 vss 54 vss 96 vss 138 vss 13 dq9 55 dq20 97 dq45 139 dq56 14 dq10 56 dq21 98 dq46 140 dq57 15 dq11 57 dq22 99 dq47 141 dq58 16 dq12 58 dq23 100 dq48 142 dq59 17 dq13 59 vcc 101 dq49 143 vcc 18 vcc 60 dq24 102 vcc 144 dq60 19 dq14 61 nc 103 dq50 145 nc 20 dq15 62 nc 104 dq51 146 nc 21 dq16 63 nc 105 dq52 147 nc 22 dq17 64 nc 106 dq53 148 nc 23 vss 65 dq25 107 vss 149 dq61 24 nc 66 dq26 108 nc 150 dq62 25 nc 67 dq27 109 nc 151 dq63 26 vcc 68 vss 110 vcc 152 vss 2 7 we0 6 9 dq 28 111 n c 15 3 d q6 4 28 cas0 70 dq29 112 nc 154 dq65 29 nc 71 dq30 113 nc 155 dq66 30 ras0 72 dq31 114 nc 156 dq67 31 oe0 73 vcc 115 nc 157 vcc 32 vss 74 dq32 116 vss 158 dq68 33 a0 75 dq33 117 a1 159 dq69 34 a2 76 dq34 118 a3 160 dq70 35 a4 77 dq35 119 a5 161 dq71 36 a6 78 vss 120 a7 162 vss 37 a8 79 pd1 121 a9 163 pd2 38 a10 80 pd3 122 a11 164 pd4 39 a12 81 pd5 123 nc 165 pd6 40 vcc 82 pd7 124 vcc 166 pd8 41 nc 83 id0 (vss) 125 nc 167 id1 (vss) 42 nc 84 vcc 126 b0 168 vcc semiconductor group 4 hym72v1600/10gs-50/-60 16m x 72-ecc module block diagram i/o1-i/o4 d0 i/o1-i/o4 d1 i/o1-i/o4 d2 i/o1-i/o4 d3 i/o1-i/o4 d4 i/o1-i/o4 d5 i/o1-i/o4 d6 i/o1-i/o4 d7 i/o1-i/o4 d8 i/o1-i/o4 d9 i/o1-i/o4 d10 i/o1-i/o4 d11 i/o1-i/o4 d12 i/o1-i/o4 d13 i/o1-i/o4 d14 i/o1-i/o4 d15 i/o1-i/o4 d16 i/o1-i/o4 d17 d0 - d8 d9 - d17 d0 - d17 dq0-dq3 dq4-dq7 ras0 cas0 we0 oe0 dq8-dq11 dq12-dq15 dq16-dq19 dq20-dq23 dq24-dq27 dq28-dq31 dq32-dq35 dq36-dq39 dq40-dq43 ras2 cas4 we2 oe2 dq44-dq47 dq48-dq51 dq52-dq55 dq56-dq59 dq60-dq63 dq64-dq67 dq68-dq71 a0 b0 a1-a12 vcc vss d0-d17, buffers vcc or vss pd1-pd8 pde semiconductor group 4 hym72v1600/10gs-50/-60 16m x 72-ecc module block diagram i/o1-i/o4 d0 i/o1-i/o4 d1 i/o1-i/o4 d2 i/o1-i/o4 d3 i/o1-i/o4 d4 i/o1-i/o4 d5 i/o1-i/o4 d6 i/o1-i/o4 d7 i/o1-i/o4 d8 i/o1-i/o4 d9 i/o1-i/o4 d10 i/o1-i/o4 d11 i/o1-i/o4 d12 i/o1-i/o4 d13 i/o1-i/o4 d14 i/o1-i/o4 d15 i/o1-i/o4 d16 i/o1-i/o4 d17 d0 - d8 d9 - d17 d0 - d17 dq0-dq3 dq4-dq7 ras0 cas0 we0 oe0 dq8-dq11 dq12-dq15 dq16-dq19 dq20-dq23 dq24-dq27 dq28-dq31 dq32-dq35 dq36-dq39 dq40-dq43 ras2 cas4 we2 oe2 dq44-dq47 dq48-dq51 dq52-dq55 dq56-dq59 dq60-dq63 dq64-dq67 dq68-dq71 a0 b0 a1-a12 vcc vss d0-d17, buffers vcc or vss pd1-pd8 pde semiconductor group 5 hym72v1600/10gs-50/-60 16m x 72-ecc module absolute maximum ratings operating temperature range ......................................................................................... 0 to + 70 c storage temperature range...................................................................................... C 55 to + 125 c input/output voltage ............................................................................... -0.5 to min (vcc+0.5, 4.6) v power supply voltage............................................................................................. C 1.0 v to + 4 .6 v power dissipation.............................................................................................................. ...... 8.3 w data out current (short circuit) ............................................................................................... . 50 ma note : stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics t a = 0 to 70 c; v cc = 3.3 v 0.3 v parameter symbol limit values unit test condition min. max. input high voltage v ih 2.0 vcc+0.5 v1) input low voltage v il C 1.0 0.8 v 1) output high voltage (lvttl) output ?h voltage level ( i out = C 2 ma) v oh 2.4 C v 1) output low voltage (lvttl) output ?l voltage level ( i out = 2 ma) v ol C 0.4 v 1) output high voltage (lvcmos) output ?h voltage level ( i out = C 100 m a) v oh vcc-0.2 C v 1) output low voltage (lvcmos) output ?l voltage level ( i out = 100 m a) v ol C 0.2 v 1) input leakage current (0 v < v in < vcc, all other pins = 0 v) i i(l) C 20 20 m a1) output leakage current (do is disabled, 0 v < v out < vcc) i o(l) C 20 20 m a1) average v cc supply current: -50 version -60 version (ras , cas , address cycling, t rc = t rc min.) i cc1 C C 2000 1800 ma ma 2) 3) 4) standby v cc supply current (ras = cas = v ih, one address change) i cc2 C50maC semiconductor group 5 hym72v1600/10gs-50/-60 16m x 72-ecc module absolute maximum ratings operating temperature range ......................................................................................... 0 to + 70 c storage temperature range...................................................................................... C 55 to + 125 c input/output voltage ............................................................................... -0.5 to min (vcc+0.5, 4.6) v power supply voltage............................................................................................. C 1.0 v to + 4 .6 v power dissipation.............................................................................................................. ...... 8.3 w data out current (short circuit) ............................................................................................... . 50 ma note : stresses above those listed under "absolute maximum ratings" may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc characteristics t a = 0 to 70 c; v cc = 3.3 v 0.3 v parameter symbol limit values unit test condition min. max. input high voltage v ih 2.0 vcc+0.5 v1) input low voltage v il C 1.0 0.8 v 1) output high voltage (lvttl) output ?h voltage level ( i out = C 2 ma) v oh 2.4 C v 1) output low voltage (lvttl) output ?l voltage level ( i out = 2 ma) v ol C 0.4 v 1) output high voltage (lvcmos) output ?h voltage level ( i out = C 100 m a) v oh vcc-0.2 C v 1) output low voltage (lvcmos) output ?l voltage level ( i out = 100 m a) v ol C 0.2 v 1) input leakage current (0 v < v in < vcc, all other pins = 0 v) i i(l) C 20 20 m a1) output leakage current (do is disabled, 0 v < v out < vcc) i o(l) C 20 20 m a1) average v cc supply current: -50 version -60 version (ras , cas , address cycling, t rc = t rc min.) i cc1 C C 2000 1800 ma ma 2) 3) 4) standby v cc supply current (ras = cas = v ih, one address change) i cc2 C50maC semiconductor group 6 hym72v1600/10gs-50/-60 16m x 72-ecc module average v cc supply current during ras only refresh cycles: -50 version -60 version (ras cycling, cas = v ih , t rc = t rc min.) i cc3 C C 2000 1800 ma ma 2) 4) average v cc supply current during fast page mode: -50 version -60 version (ras = v il, cas , address cycling t pc = t pc min.) i cc4 C C 1550 1400 ma ma 2) 3) 4) standby v cc supply current (ras = cas = v cc C 0.2 v, v16one address change) i cc5 C30maC average v cc supply current during cas -before-ras refresh mode: -50 version -60 version (ras , cas cycling , t rc = t rc min.) i cc6 C C 2000 1800 ma ma 2) 4) parameter symbol limit values unit test condition min. max. semiconductor group 6 hym72v1600/10gs-50/-60 16m x 72-ecc module average v cc supply current during ras only refresh cycles: -50 version -60 version (ras cycling, cas = v ih , t rc = t rc min.) i cc3 C C 2000 1800 ma ma 2) 4) average v cc supply current during fast page mode: -50 version -60 version (ras = v il, cas , address cycling t pc = t pc min.) i cc4 C C 1550 1400 ma ma 2) 3) 4) standby v cc supply current (ras = cas = v cc C 0.2 v, v16one address change) i cc5 C30maC average v cc supply current during cas -before-ras refresh mode: -50 version -60 version (ras , cas cycling , t rc = t rc min.) i cc6 C C 2000 1800 ma ma 2) 4) parameter symbol limit values unit test condition min. max. semiconductor group 7 hym72v1600/10gs-50/-60 16m x 72-ecc module ac characteristics (note: 5,6,7,8) t a = 0 to 70 c, v cc = 3.3 0.3 v parameter symbol -50 -60 unit note min. max. min. max. common parameters random read or write cycle time t rc 90 C 110 C ns ras precharge time t rp 30 C 40 C ns ras pulse width t ras 50 100k 60 100k ns cas pulse width t cas 13 100k 15 100k ns row address setup time t asr 5C5Cns 9 row address hold time t rah 8C8Cns 10 column address setup time t asc 2C2Cns 11 column address hold time t cah 15 C 15 C ns 9 ras to cas delay time t rcd 16 32 18 40 12 ras to column address delay time t rad 11 20 13 25 ns 12 ras hold time t rsh 18 C 20 C ns 9 cas hold time t csh 48 C 58 C ns 10 cas to ras precharge time t crp 10 C 10 C ns 9 transition time (rise and fall) t t 330330ns 7 refresh period t ref C128C128ms read cycle access time from ras t rac C50C60ns 13,14 access time from cas t cac C18C20ns 9,13,14 access time from column address t aa C30C35ns 9,13, 15 oe access time t oea C18C20ns 9,13 column address to ras lead time t ral 30 C 35 C ns 9 read command setup time t rcs 2C2Cns 11 read command hold time t rch 2C2Cns 11,16 read command hold time referenced to ras t rrh 0C0Cns 16 cas to output in low-z t clz 2C2Cns 11,13 output buffer turn-off delay t off C18C20ns 9,17 semiconductor group 7 hym72v1600/10gs-50/-60 16m x 72-ecc module ac characteristics (note: 5,6,7,8) t a = 0 to 70 c, v cc = 3.3 0.3 v parameter symbol -50 -60 unit note min. max. min. max. common parameters random read or write cycle time t rc 90 C 110 C ns ras precharge time t rp 30 C 40 C ns ras pulse width t ras 50 100k 60 100k ns cas pulse width t cas 13 100k 15 100k ns row address setup time t asr 5C5Cns 9 row address hold time t rah 8C8Cns 10 column address setup time t asc 2C2Cns 11 column address hold time t cah 15 C 15 C ns 9 ras to cas delay time t rcd 16 32 18 40 12 ras to column address delay time t rad 11 20 13 25 ns 12 ras hold time t rsh 18 C 20 C ns 9 cas hold time t csh 48 C 58 C ns 10 cas to ras precharge time t crp 10 C 10 C ns 9 transition time (rise and fall) t t 330330ns 7 refresh period t ref C128C128ms read cycle access time from ras t rac C50C60ns 13,14 access time from cas t cac C18C20ns 9,13,14 access time from column address t aa C30C35ns 9,13, 15 oe access time t oea C18C20ns 9,13 column address to ras lead time t ral 30 C 35 C ns 9 read command setup time t rcs 2C2Cns 11 read command hold time t rch 2C2Cns 11,16 read command hold time referenced to ras t rrh 0C0Cns 16 cas to output in low-z t clz 2C2Cns 11,13 output buffer turn-off delay t off C18C20ns 9,17 semiconductor group 8 hym72v1600/10gs-50/-60 16m x 72-ecc module output buffer turn-off delay from oe t oez C18C20ns 9,17 cas delay time from din t dzc 0C0Cns 18 data to oe low delay t dzo 0C0Cns 18 cas high to data delay t cdd 18 C 20 C ns 9,19 oe high to data delay t odd 18 C 20 C ns 9,19 write cycle write command hold time t wch 13 C 15 C ns 9 write command pulse width t wp 8C10Cns write command setup time t wcs 2C2Cns 11,20 write command to ras lead time t rwl 18 C 20 C ns 9 write command to cas lead time t cwl 13 C 15 C ns data setup time t ds -2 C -2 C ns 10,21 data hold time t dh 15 C 15 C ns 9,21 read-modify-write cycle read-write cycle time t rwc 131 C 155 C ns 9 ras to we delay time t rwd 70 C 82 C ns 11,21 cas to we delay time t cwd 33 C 37 C ns 11,21 column address to we delay time t awd 45 C 52 C ns 11,21 oe command hold time t oeh 11 C 13 C ns 10 fast page mode cycle fast page mode cycle time t pc 35 C 40 C ns cas precharge time t cp 10 C 10 C ns access time from cas precharge t cpa C35C40ns 9,13 ras pulse width t ras 50 200k 60 200k ns cas precharge to ras delay t rhcp 35 C 40 C ns 9 ac characteristics (contd)(note: 5,6,7,8) t a = 0 to 70 c, v cc = 3.3 0.3 v parameter symbol -50 -60 unit note min. max. min. max. semiconductor group 8 hym72v1600/10gs-50/-60 16m x 72-ecc module output buffer turn-off delay from oe t oez C18C20ns 9,17 cas delay time from din t dzc 0C0Cns 18 data to oe low delay t dzo 0C0Cns 18 cas high to data delay t cdd 18 C 20 C ns 9,19 oe high to data delay t odd 18 C 20 C ns 9,19 write cycle write command hold time t wch 13 C 15 C ns 9 write command pulse width t wp 8C10Cns write command setup time t wcs 2C2Cns 11,20 write command to ras lead time t rwl 18 C 20 C ns 9 write command to cas lead time t cwl 13 C 15 C ns data setup time t ds -2 C -2 C ns 10,21 data hold time t dh 15 C 15 C ns 9,21 read-modify-write cycle read-write cycle time t rwc 131 C 155 C ns 9 ras to we delay time t rwd 70 C 82 C ns 11,21 cas to we delay time t cwd 33 C 37 C ns 11,21 column address to we delay time t awd 45 C 52 C ns 11,21 oe command hold time t oeh 11 C 13 C ns 10 fast page mode cycle fast page mode cycle time t pc 35 C 40 C ns cas precharge time t cp 10 C 10 C ns access time from cas precharge t cpa C35C40ns 9,13 ras pulse width t ras 50 200k 60 200k ns cas precharge to ras delay t rhcp 35 C 40 C ns 9 ac characteristics (contd)(note: 5,6,7,8) t a = 0 to 70 c, v cc = 3.3 0.3 v parameter symbol -50 -60 unit note min. max. min. max. semiconductor group 9 hym72v1600/10gs-50/-60 16m x 72-ecc module fast page mode read-modify-write cycle fast page mode read-write cycle time t prwc 73 C 82 C ns 11 cas precharge to we t cpwd 50 C 57 C ns 11,21 cas -before-ras refresh cycle cas setup time t csr 7C7Cns 11 cas hold time t chr 8C8Cns10 ras to cas precharge time t rpc 5C5Cns write to ras precharge time t wrp 12 C 12 C ns 11 write hold time referenced to ras t wrh 8C8Cns10 presence detect read cycle pde to valid presence detect data t pd C10C10ns pde inactive to presence detects inactive t pdoff 010010ns ac characteristics (contd)(note: 5,6,7,8) t a = 0 to 70 c, v cc = 3.3 0.3 v parameter symbol -50 -60 unit note min. max. min. max. semiconductor group 9 hym72v1600/10gs-50/-60 16m x 72-ecc module fast page mode read-modify-write cycle fast page mode read-write cycle time t prwc 73 C 82 C ns 11 cas precharge to we t cpwd 50 C 57 C ns 11,21 cas -before-ras refresh cycle cas setup time t csr 7C7Cns 11 cas hold time t chr 8C8Cns10 ras to cas precharge time t rpc 5C5Cns write to ras precharge time t wrp 12 C 12 C ns 11 write hold time referenced to ras t wrh 8C8Cns10 presence detect read cycle pde to valid presence detect data t pd C10C10ns pde inactive to presence detects inactive t pdoff 010010ns ac characteristics (contd)(note: 5,6,7,8) t a = 0 to 70 c, v cc = 3.3 0.3 v parameter symbol -50 -60 unit note min. max. min. max. semiconductor group 10 hym72v1600/10gs-50/-60 16m x 72-ecc module notes: 1) all voltages are referenced to vss. 2) icc1, icc3, icc4 and icc6 and icc7 depend on cycle rate. 3) icc1 and icc4 depend on output loading. specified values are measured with the output open. 4) address can be changed once or less while ras = vil.in the case of icc4 it can be changed once or less during a fast page mode cycle ( tpc). 5) an initial pause of 100 m s is required after power-up followed by 8 ras-only-refresh cycles, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume tt = 5 ns. 7) vih (min.) and vil (max.) are reference levels for measuring timing of input signals. also, transition times are measured between vih and vil. 8) the specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (cas , we , oe , addresses) maximum delay, no pulse shrinkage to the dram device timings. the data and ras signals are not buffered, which preserves the drams access specification of 50ns and 60ns. 9) a +5ns timing skew from the dram to the module resulted from the addition of line drivers. 10) a -2ns timing skew from the dram to the module resulted from the addition of line drivers. 11) a +2ns timing skew from the dram to the module resulted from the addition of line drivers. 12) a -2ns (min.) and a -5ns (max.) timing skew from the dram to the module resulted from the addition of line drivers. 13) measured with the specified current load and 100 pf at voh = 2.0 v and vol = 0.8 v. 14) operation within the trcd (max.) limit ensures that trac (max.) can be met. trcd (max.) is specified as a reference point only: if trcd is greater than the specified trcd (max.) limit, then access time is controlled by tcac. 15) operation within the trad (max.) limit ensures that trac (max.) can be met. trad (max.) is specified as a reference point only: if trad is greater than the specified trad (max.) limit, then access time is controlled by taa. 16) either trch or trrh must be satisfied for a read cycle. 17) toff (max.) and toez (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 18) either tdzc or tdzo must be satisfied. 19) either tcdd or todd must be satisfied. 20) twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs > twcs (min.), the cycle is an early write cycle and the i/o pin will remain open-circuit (high impedance) through the entire cycle; if trwd > trwd (min.), tcwd > tcwd (min.), tawd > tawd (min.) and tcpwd > tcpwd (min.) , the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 21) these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read- modify-write cycles. semiconductor group 10 hym72v1600/10gs-50/-60 16m x 72-ecc module notes: 1) all voltages are referenced to vss. 2) icc1, icc3, icc4 and icc6 and icc7 depend on cycle rate. 3) icc1 and icc4 depend on output loading. specified values are measured with the output open. 4) address can be changed once or less while ras = vil.in the case of icc4 it can be changed once or less during a fast page mode cycle ( tpc). 5) an initial pause of 100 m s is required after power-up followed by 8 ras-only-refresh cycles, before proper device operation is achieved. in case of using internal refresh counter, a minimum of 8 cas -before-ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume tt = 5 ns. 7) vih (min.) and vil (max.) are reference levels for measuring timing of input signals. also, transition times are measured between vih and vil. 8) the specified timings include buffer, loading and skew delay adders: 2ns minimum, 5ns (cas , we , oe , addresses) maximum delay, no pulse shrinkage to the dram device timings. the data and ras signals are not buffered, which preserves the drams access specification of 50ns and 60ns. 9) a +5ns timing skew from the dram to the module resulted from the addition of line drivers. 10) a -2ns timing skew from the dram to the module resulted from the addition of line drivers. 11) a +2ns timing skew from the dram to the module resulted from the addition of line drivers. 12) a -2ns (min.) and a -5ns (max.) timing skew from the dram to the module resulted from the addition of line drivers. 13) measured with the specified current load and 100 pf at voh = 2.0 v and vol = 0.8 v. 14) operation within the trcd (max.) limit ensures that trac (max.) can be met. trcd (max.) is specified as a reference point only: if trcd is greater than the specified trcd (max.) limit, then access time is controlled by tcac. 15) operation within the trad (max.) limit ensures that trac (max.) can be met. trad (max.) is specified as a reference point only: if trad is greater than the specified trad (max.) limit, then access time is controlled by taa. 16) either trch or trrh must be satisfied for a read cycle. 17) toff (max.) and toez (max.) define the time at which the outputs achieve the open-circuit condition and are not referenced to output voltage levels. 18) either tdzc or tdzo must be satisfied. 19) either tcdd or todd must be satisfied. 20) twcs, trwd, tcwd, tawd and tcpwd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if twcs > twcs (min.), the cycle is an early write cycle and the i/o pin will remain open-circuit (high impedance) through the entire cycle; if trwd > trwd (min.), tcwd > tcwd (min.), tawd > tawd (min.) and tcpwd > tcpwd (min.) , the cycle is a read-write cycle and i/o pins will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of the i/o pins (at access time) is indeterminate. 21) these parameters are referenced to cas leading edge in early write cycles and to we leading edge in read- modify-write cycles. semiconductor group 11 hym72v1600/10gs-50/-60 16m x 72-ecc module l-dim-168-7 module package (dual read-out, single in-line memory module) 133,35 1 84 17,78 detail of contacts 1.27 2.54 min 0.25 max +/- 0.05 10 11 40 41 85 95 96 * ) preliminary drawing 168 3,0 127,35 1.0 124 125 16mx72 3.3v dm168-7.wmf 38.1 *) 9 mm max for modules assembled with soj-devices 4 mm max. for modules assemlbed with tsopii-devices semiconductor group 11 hym72v1600/10gs-50/-60 16m x 72-ecc module l-dim-168-7 module package (dual read-out, single in-line memory module) 133,35 1 84 17,78 detail of contacts 1.27 2.54 min 0.25 max +/- 0.05 10 11 40 41 85 95 96 * ) preliminary drawing 168 3,0 127,35 1.0 124 125 16mx72 3.3v dm168-7.wmf 38.1 *) 9 mm max for modules assembled with soj-devices 4 mm max. for modules assemlbed with tsopii-devices |
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